Packaging board and manufacturing method therefor, semiconductor module and manufacturing method therefor, and portable device

ABSTRACT

A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2007-119388, filed on Apr. 27,2007, and Japanese Patent Application No. 2008-099483, filed on Apr. 7,2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a packaging board and a manufacturingmethod therefor, a semiconductor module and a manufacturing methodtherefor, and a portable device.

2. Description of the Related Art

In recent years, along with the on-going downsizing and functionalsophistication of electronic devices, there has been an ever-growingdemand for smaller circuit devices to be incorporated into electronicdevices. One of known ways to meet such a demand is to narrow the pitchof external connection electrodes of a circuit device. But because ofthe size of solder bumps themselves used as the electrodes and theformation of bridges at soldering, there has existed a limit to thedownsizing by narrowing the pitch of the external connection electrodesof a circuit device. For further downsizing of a circuit device,therefore, there is a technology conceived for rearrangement of externalconnection electrodes by forming a rewiring for a circuit device.

In general, when the rewiring is formed in the circuit device, anopening by which to provide a via contact for an insulating layer on anelectrode pad is formed in order to retrieve externally a signal sentfrom a circuit element within the circuit device via the electrode pad.In the conventional practice, a method is conceived where the formationof such an opening is done by laser irradiation. However, since thecircuit element is placed below the electrode pad, it is desired thatsuch an opening be formed without being exposed to high temperature asmuch as possible. As one of known methods to resolve this problem is amethod for manufacturing a semiconductor device by the laser irradiationfollowed by dry etching.

Nevertheless, in the above-described method, the electrode pad exposedat the final stage in the dry etching is exposed to plasma atmospherewhile the effect of heat by the laser irradiation can be suppressed. Asa result, the circuit elements, such as transistors, which are connectedto the electrode pad may possibly be charged up. Accordingly, the deviceperformance deteriorates due to the charge-up phenomenon and thereforethe reliability of circuit elements drops.

SUMMARY OF THE INVENTION

In order to solve the foregoing problems, a method, for manufacturing asemiconductor module, according to the method includes: a first processof forming a conductor on one face of an insulating layer; a secondprocess of exposing the conductor from the other face of the insulatinglayer; a third process of providing a first wiring layer on an exposedarea of the conductor and on the other face of the insulating layer; afourth process of preparing a substrate on which a circuit element isformed wherein a second wiring is formed on the substrate; and a fifthprocess of embedding the conductor in the insulating layer bypress-bonding the insulating layer and the substrate in a state wherethe conductor on which the first wiring layer is provided by the thirdprocess is disposed counter to the second wiring layer.

By employing this embodiment, the conductor is exposed from the otherface of the insulating layer before the insulating layer is press-bondedto the substrate on which a circuit element is formed. This process doesnot give damage to the circuit element. Also, by employing this method,the conductor is formed on one face of the insulating layer and, at thesame time, is exposed from the other face of the insulating layer. Andthe first wiring layer is provided in a position where the conducive isexposed, and the first wiring layer is also provided on the face of theinsulating layer. Accordingly, the conductor is firmly fixed to theinsulating layer via the first wiring layer. As a result, when theconductor is embedded in the insulating layer by press-bonding theinsulating layer and the substrate in a state where the conductor andthe second wiring layer are disposed counter to each other, theconductor is less likely to be displaced.

Another embodiment of the present invention relates also to a method formanufacturing a semiconductor module. This method includes: a firstprocess of forming a conductor on one of faces of an insulating layerwhich contains fibrous filler material whose coefficient of thermalexpansion is small than that of the insulating layer, wherein thefibrous filler material is arranged so that a direction of fibersthereof intersects with a thickness direction of the insulating layer; asecond process of exposing the conductor from the other face of theinsulating layer; a third process of providing a first wiring layer onan exposed area of the conductor and on the other face of the insulatinglayer; a fourth process of preparing a substrate on which a circuitelement is formed wherein a second wiring is formed on the substrate;and a fifth process of embedding the conductor in the insulating layerby press-bonding the insulating layer and the substrate in a state wherethe conductor on which the first wiring layer is provided by the thirdprocess is disposed counter to the second wiring layer.

By employing this embodiment, the conductor is exposed from the otherface of the insulating layer before the insulating layer is press-bondedto the substrate on which a circuit element is formed. This process doesnot give damage to the circuit element. Also, by employing this method,the conductor is formed on one face of the insulating layer and, at thesame time, is exposed from the other face of the insulating layer. Andthe first wiring layer is provided in a position where the conducive isexposed, and the first wiring layer is also provided on the face of theinsulating layer. Accordingly, the conductor is firmly fixed to theinsulating layer via the first wiring layer. As a result, when theconductor is embedded in the insulating layer by press-bonding theinsulating layer and the substrate in a state where the conductor andthe second wiring layer are disposed counter to each other, theconductor is less likely to be displaced. Also, according to thisembodiment, the fibrous filler material whose coefficient of thermalexpansion is smaller than that of the insulating layer is contained inthe insulating layer. Thus, the deformation of the insulating layercaused when the thermal stress is applied to the semiconductor modulecan be restricted. The fibrous filler material is curved toward thefirst wiring layer by the conductor penetrating through the insulatinglayer. As a result, its restorative force works to press the conductoragainst the second wiring layer to achieve adhesion therebetween.

Still another embodiment of the present invention relates to a methodfor manufacturing a packaging board. This method includes: a firstprocess of forming a conductor on one of faces of an insulating layer; asecond process of exposing the conductor from the other face of theinsulating layer; and a third process of providing a wiring layer on anexposed area of the conductor and on the other face of the insulatinglayer. A means for roughening an exposed face of the conductor is usedin the second process. By employing this embodiment, the adhesionbetween the conductor and the wiring layer improves.

Still another embodiment of the present invention relates to a packagingboard. This packaging board comprises: an insulating layer; a conductorformed on one of faces of the insulating layer; and a wiring layerprovided on the other face of the insulating layer and a penetrationportion penetrating to the conductor from the other face thereof. Anarithmetic mean roughness Ra of the exposed face of the conductor incontact with the wiring layer is 2 to 50 μm. By employing thisembodiment, the adhesion between the conductor and the wiring layerimproves.

Still another embodiment of the present invention relates to asemiconductor module. This semiconductor module comprises: an insulatinglayer; a first wiring layer provided on the insulating layer; asubstrate on which a circuit element is formed; a second wiring layerformed on a face of the substrate; and a conductor, embedded in theinsulating layer, which electrically connects the first wiring layer tothe second layer. The conductor is such that an arithmetic meanroughness Ra of a face thereof in contact with the first wiring layer is2 to 50 μm.

By employing this embodiment, the adhesion between the conductor and thefirst wiring layer improves. If the arithmetic mean roughness Ra of theface in contact therewith is small, the adhesion between the conductorand the first wiring layer will not be enough. If the arithmetic meanroughness Ra is too high, a plated layer will grow abnormally and theconcentration of electric field will occur when the first wiring layeris formed on an exposed area of the conductor by the plating. This maycause faulty conduction.

Still another embodiment of the present invention relates also to asemiconductor module. This semiconductor module comprises: an insulatinglayer which contains fibrous filler material whose coefficient ofthermal expansion is smaller than that of the insulating layer, thefibrous filler material being arranged so that a direction of fibersthereof intersects with a thickness direction of the insulating layer; afirst wiring layer provided on the insulating layer; a substrate onwhich a circuit element is formed; a second wiring layer formed on aface of the substrate; and a conductor, embedded in the insulatinglayer, which electrically connects the first wiring layer to the secondlayer. The fibrous filler material has a smaller coefficient of thermalexpansion than that of the insulating layer, and the filler material iscurved toward the first insulating layer in the vicinity of theconductor; and the conductor is such that an arithmetic mean roughnessRa of a face thereof in contact with the first wiring layer is 2 to 50μm.

By employing this embodiment, the adhesion between the conductor and thefirst wiring layer improves. Also, according to this embodiment, thefibrous filler material whose coefficient of thermal expansion issmaller than that of the insulating layer is contained in the insulatinglayer. Thus, the deformation of the insulating layer caused when thethermal stress is applied to the semiconductor module can be suppressed.The fibrous filler material is curved toward the first wiring layer bythe conductor penetrating through the insulating layer. As a result, itsrestorative force works to press the conductor against the second wiringlayer to achieve adhesion therebetween.

Still another embodiment of the present invention relates to a portabledevice. This portable device mounts a semiconductor module according toany one of the above-described embodiments.

It is to be noted that any arbitrary combinations or rearrangement, asappropriate, of the aforementioned constituting elements and so forthare all effective as and encompassed by the embodiments of the presentinvention.

Moreover, this summary of the invention does not necessarily describeall necessary features so that the invention may also be sub-combinationof these described features.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described by way of examples only, withreference to the accompanying drawings which are meant to be exemplary,not limiting, and wherein like elements are numbered alike in severalFigures in which:

FIG. 1 is a schematic cross-sectional view illustrating a structure of asemiconductor module according to a first embodiment of the presentinvention;

FIGS. 2A to 2C are schematic cross-sectional views for explaining afirst process in a method for manufacturing a semiconductor moduleaccording to a first embodiment of the present invention;

FIGS. 3A and 3B are schematic cross-sectional views for explaining asecond process and a third process in a method for manufacturing asemiconductor module according to a first embodiment of the presentinvention;

FIGS. 4A and 4B are schematic cross-sectional views for explaining afourth process and a fifth process in a method for manufacturing asemiconductor module according to a first embodiment of the presentinvention;

FIG. 5 is a top view showing that a conductive bump is exposed from theother face of a insulating layer by laser irradiation;

FIG. 6 is a schematic cross-sectional view illustrating a structure of asemiconductor module according to a second embodiment of the presentinvention;

FIGS. 7A to 7C are schematic cross-sectional views for explaining afirst process in a method for manufacturing a semiconductor moduleaccording to a second embodiment of the present invention;

FIGS. 8A and 8B are schematic cross-sectional views for explaining asecond process and a third process in a method for manufacturing asemiconductor module according to a second embodiment of the presentinvention;

FIGS. 9A and 9B are schematic cross-sectional views for explaining afourth process and a fifth process in a method for manufacturing asemiconductor module according to a second embodiment of the presentinvention;

FIG. 10 illustrates a structure of a mobile phone according to a thirdembodiment of the present invention; and

FIG. 11 is a partial cross-sectional view of a mobile phone shown inFIG. 10.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described by reference to the preferredembodiments. This does not intend to limit the scope of the presentinvention, but to exemplify the invention.

The embodiments will now be described with reference to drawings. Notethat in all of the Figures the same components are given the samereference numerals and the repeated description thereof is omitted asappropriate.

First Embodiment [Structure of a Semiconductor Module]

FIG. 1 is a schematic cross-sectional view illustrating a structure of asemiconductor module according to a first embodiment of the presentinvention. As shown in FIG. 1, a semiconductor module 10 according tothe first embodiment includes a semiconductor substrate 12 with apredetermined electric circuit or a circuit element such as MOSFET (notshown) formed by a known technique on a surface S (upper-face side)thereof, an electrode 14 of the circuit element, which is part of asecond wiring layer formed on the surface S (especially in theperipheral part) serving as a mounting face of the semiconductorsubstrate 12, an insulating layer 16 disposed on the electrode 14, afirst wiring layer 18 disposed on the insulating layer 16, and aconductive bump 20 which serves as a conductor electrically connectingthe electrode 14 to the first wiring layer 18 in a state where it isembedded with the insulating layer 16.

Formed on the face of the semiconductor substrate 12 is a protectivefilm 22 in such a manner that it has a predetermined region exposing theelectrode 14. To widen the pitch of adjacent electrodes 14, a rewiringpattern 18 a is formed on the insulating layer 16 which is provided onthe top of the electrode 14 and the protective film 22. Connectionbetween the electrode 14 and the rewiring pattern 18 a is made via theconductive bump 20 in contact with the exposed surface of the electrode14 and a via contact 18 b connected to this conductive bump 20. Providedon a predetermined region of the rewiring pattern 18 a is a solder bump24, which serves as an external connection electrode, and the rewiringpattern 18 a is covered by a solder resist layer 26 except in the regionwhere the solder bump 24 is provided.

More specifically, the insulating layer 16 is disposed above the surfaceS of the semiconductor substrate 12, and the thickness thereof is, forinstance, about 80 μm. The insulating layer 16 is formed of B-stageresin. It is desirable that a thermosetting resin, such as polyimideresin, epoxy resin, phenol resin and BT resin, be a material used forthe insulating layer 16. Alternatively, the insulating layer 16 may beformed of a material that develops plastic flow under pressure. An epoxythermosetting resin is one example of the material that develops plasticflow under pressure. The epoxy thermosetting resin to form theinsulating layer 16 is more preferably a material that has a viscosityof about 1 kPa·s at a temperature of 160° C. and a pressure of 8 MPa.When placed under a pressure of 15 MPa at a temperature of 160° C., theviscosity of this resin material drops to about ⅛ of that without thepressurization.

The resin may be a type of film in which woven glass fiber isimpregnated with resin. Or the insulating layer 16 may be a film addedwith a filler of about 2 to 10 μm diameter. The filler material ispreferably alumina (Al₂O₃), silica (SiO₂), aluminum nitride (AlN),silicon nitride (SiN), boron nitride (BN) or the like. The filling rateof the filler in weight is preferably about 30 to 80%. The conductivebump 20 may be made of a metal such as copper (Cu) or aluminum (Al).

The height of the conductive bump 20 is, for instance, about 10 μm. Theconductive bump 20 according to the first embodiment, which is disposedas a circular truncated cone (trapezoidal in cross section), has a tipend, which is in parallel with the contact face of the electrode 14, anda side face part 20 a, which is formed increasingly smaller in diameter(size) closer to the tip end. That is, the conductive bump 20 has a sideface part 20 a formed at an obtuse angle with the face in contact withthe surface S of the semiconductor substrate 12. In other words, theconductive bump 20 is formed in such a manner that the area of crosssection in parallel with the surface S of the semiconductor substrate 12increases as it approaches the first wiring layer 18 from the electrode14. The diameter of the tip end of the conductive bump 20 and thediameter of the face in contact with the first wiring layer 18 are about80 μmφ and about 100 μmφ, respectively. The conductive bump 20 isdisposed in a position corresponding to the electrode 14. And the tipend of the conductive bump 20 is so formed that it comes in directcontact with the electrode 14. Note that the height of the conductivebump 20 may be selected from the range of about 5 to 20 μm.

The rewiring pattern 18 a is formed on the insulating layer 16, and thethickness thereof is, for instance, about 20 μm. The rewiring pattern 18a, which is formed of a metal such as copper (Cu), is electricallyconnected to the conductive bump 20 via the via contact 18 b, which isdisposed within an opening 28 in the insulating layer 16. Here, thewidth of the opening 28 is about 100 μm. The via contact 18 b isdisposed in such a manner as to cover the inner surface of the opening28, and is formed integrally with the rewiring pattern 18 a. It is to benoted that because of the presence of the conductive bump 20 on theelectrode 14, the depth of the via contact 18 b (opening 28) is about 70μm, which can be shallower than when the via contact (opening) is formeddirectly on the electrode 14.

As described above, the semiconductor module 10 according to the presentembodiment has the rewiring pattern 18 a formed to be coupled with theelectrode 14 formed on the surface S of the semiconductor substrate 12via the conductive bump 20 and the via contact 18 b, so thatrearrangement of the solder bump 24, which is an external connectionelectrode, can be effected.

(Manufacturing Method of Semiconductor Module)

Now, referring to FIGS. 2A to 4B, a method for manufacturing asemiconductor module according to the first embodiment will bedescribed. FIGS. 2A to 2C are schematic cross-sectional views forexplaining a first process in the method for manufacturing asemiconductor module according to the first embodiment. FIGS. 3A and 3Bare schematic cross-sectional views for explaining a second process anda third process in the method for manufacturing a semiconductor moduleaccording to the first embodiment. FIGS. 4A and 4B are schematiccross-sectional views for explaining a fourth process and a fifthprocess in the method for manufacturing a semiconductor module accordingto the first embodiment.

First, as shown in FIG. 2A, a copper layer 32 of about 10 μm thicknessis formed on one face of an insulating layer 16 of about 80 μmthickness, which is made of an epoxy thermosetting resin, using anelectroless plating and an electrolytic plating. Next, as shown in FIG.2B, a resist mask 34 is formed in a conductive bump forming area on thecopper layer 32, using an ordinary lithography method. Here, theconductive bump forming area corresponds to the position of theelectrode 14 of the semiconductor substrate 12 shown in FIG. 1.

Now, as shown in FIG. 2C, a conductive bump 20 having a predeterminedcircular truncated cone shape is formed by a wet etching process using achemical and the resist mask 34 as the mask, and then the resist mask 34is removed. At this time, the conductive bump 20 is so formed as to havea side face part 20 a, which is increasingly smaller in diameter (size)closer to the tip end. That is, the conductive bump 20 has a side facepart 20 a formed at an acute angle with the face in contact with thesurface of the insulating layer 16. In other words, the conductive bump20 is formed in such a manner that the area of cross section parallel tothe surface of the insulating layer 16 decreases in the directionperpendicular to the surface of the insulating layer 16. Thus, by thefirst process according to the first embodiment as illustrated in FIGS.2A to 2C, the conductive bump 20 can be formed on one face of theinsulating layer 16.

In the manufacturing method of a semiconductor module 10 according tothe first embodiment, the height of the conductive bump 20 is about 10μm, the diameter of the tip end of the conductive bump 20 is about 80μmφ, and the diameter of the face at which the conductive bump 20 is incontact with the insulating layer 16 is about 100 μmφ. In each step ofthe above-described process, care is exercised not to heat to thethermosetting temperature so that the insulating layer 16, which is madeof an epoxy thermosetting resin, is maintained in a half-cured (fluid)state without being completely thermally-cured.

Next, a description will be given of the second process, in which theconductive bump 20 is exposed from the other face of the insulatinglayer 16, and the third process, in which a first wiring layer 18 isformed on the exposed portion of the conductive bump 20 and on the otherface of insulating layer 16.

As shown in FIG. 3A, an opening 28 is formed by laser irradiation fromabove the insulating layer 16 in a manner such that the conductive bump20 is exposed. That is, the opening 28 is a penetration portion thatpenetrates to the conductive bump 20 from the top face of the insulatinglayer 16. The laser irradiation here may use carbon dioxide gas laser,for instance. The laser irradiation is performed in two stages. Onestage uses first irradiation conditions where relevant part of theinsulating layer 16 is removed to an arbitrary depth by a beam whoseenergy density is high. The other stage uses second irradiationconditions where the shape of a via side wall is adjusted by a beamwhose energy density is low. To be more precise, the power at processingpoint may be 1.0 to 5.0 W and the pulse number may be 5 to 50 as thefirst irradiation conditions. As the second irradiation conditions, thepower at processing point may be 0.1 to 0.5 W, the pulse number may be1, the beam diameter may be 10 to 30 μm, the shift amount may be 5 to 20μm, and the pitch may be 1 to 10 μm. Thereby, the opening 28 having atapered side wall whose diameter decreases as it approaches theconductive bump 20 from the surface of the insulating layer 16 can beformed.

In the above-described first process, the conductive bump 20 is formedin such a manner that the area of cross section parallel to the surfaceof the insulating layer 16 decreases in the direction perpendicular tothe surface of the insulating layer 16. Therefore, the conductive bump20, which is embedded in the insulating layer 16 in the third processdescribed later, has a larger area of the portion thereof facing theupper face of the insulating layer 16 than the area of the face thereofin contact with the electrode 14. As a result, the conductive bump 20 isexposed from the other face of the insulating layer 16, which makespositioning easier for via formation with laser to expose the conductivebump 20 from the other face of the insulating layer 16. Hence, themanufacturing cost can be reduced. Thus, by the second process (exposingprocess) according to the first embodiment as illustrated in FIG. 3A,the conductive bump 20 can be exposed from the other face of theinsulating layer 16.

In the second process according to the first embodiment, the exposingface of the conductive bump 20 is subjected to roughening when theconductive bump 20 is to be exposed from the other face of theinsulating layer 16. FIG. 5 is a top view showing that the conductivebump is exposed from the other face of the insulating layer by laserirradiation.

In the first embodiment, laser is used as a means for roughening thesurface of the conductive bump 20, and the opening 28 serving as a viahole having larger diameter than the spot diameter of the laser beam isformed from the other face of the insulating layer 16 by the use of aplurality of laser irradiations and, at the same time, an exposed face20 b of the conductive bump 20 is roughened. Thereby, the formation of avia hole and the roughening processing of the exposed face 20 b of theconductive bump 20 can be done in the same process. Hence, themanufacturing cost can be reduced.

Next, as shown in FIG. 3B, a plating of copper in the thickness of about20 μm is performed on the upper face of the insulating layer 16 and onthe inner face of the opening 28 including a position where theconductive bump 20 is exposed, using an electroless plating and anelectrolytic plating, as the third process. As a result, a first wiringlayer 18 comprised of a copper plating layer having a thickness of about20 μm is formed on the insulating layer 16, and at the same time a viacontact 18 b is formed inside the opening 28. As described above, apackaging board 50 as shown in FIG. 3B is manufactured by each step ofthe aforementioned process.

The exposed face of the conductor bump 20 in the packaging board 50 isroughened wherein the face thereof exposed by the above-describedprocess corresponds to a joint between the conductive bump 20 and thefirst wiring layer 18. Hence, the adhesion to the first wiring layer 18improves and therefore the displacement of the conductive bump 20 whichmay be caused when it is embedded in the insulating layer 16 can besuppressed. It is to be noted here that in the second process theopening 28 is formed from the other face of the insulating layer 16 in amanner that an arithmetic mean roughness Ra of the exposed face of theconductive bump 20, namely the face in contact with the first wiringlayer 18, is 2 to 50 μm. As a result, the adhesion between theconductive bump 20 and the first wiring layer 18 further improves.

Next a description is given of the fourth process and the fifth process.The fourth process prepares a semiconductor substrate 12 where anelectrode 14 serving as a second wiring layer is formed on the surfaceof the substrate. In the fifth process, the insulating layer 16 and thesemiconductor substrate 12 are press-bonded together and thereby theconductive bump 20 is embedded into the insulating layer 16 while theconductive bump 20 formed on the first wiring layer 18 provided by theabove-described third process is disposed counter to the electrode 14.

First, a predetermined electric circuit or a circuit element such asMOSFET (not shown) is formed by a known technique in a region near thesurface S of the semiconductor substrate 12, which is for instance ap-type silicon substrate, and also an electrode 14 is formed by a knowntechnology in the peripheral part or the upper part thereof. Theelectrode 14 is generally made of a metal such as aluminum. Then aninsulating-type protective film 22 to protect the semiconductorsubstrate 12 is formed in a region on the surface S of the semiconductorsubstrate 12 such that a predetermined portion of the electrode 14 isexposed. The protective film 22 to be used may be a silicon dioxide film(SiO₂) or a silicon nitride film (SiN).

The thus manufactured semiconductor substrate 12 is prepared as shown inFIG. 4A, and the insulating layer 16 and the semiconductor substrate 12are stacked in a state where the conductive bump 20 formed on the firstwiring layer 18 and the electrode 14 are disposed counter to each other.Then, in this state, press-forming is performed using a press unit, sothat, as shown in FIG. 4B, the conductive bump 20 is embedded into theinsulating layer 16, thus uniting the semiconductor substrate 12, theconductive bump 20 and the insulating layer 16 into a single body(embedding process).

Here the pressure for the press-forming using the press unit is about 5MPa, and the temperature therefor is about 200° C. As a result of thispress-forming, the viscosity of the insulating layer 16 drops, and thusthe insulating layer 16 develops plastic flow. Hence, the conductivebump 20, while it is in contact with the electrode 14, is embeddedself-aligningly in the insulating layer 16. In this first embodiment,the thickness of the insulating layer 16 is about 80 μm and the heightof the conductive bump 20 is about 20 μm, so that the conductive bump 20is embedded by the press-forming into the insulating layer 16 withoutpenetrating therethrough.

Immediately following the embedding of the conductive bump 20 in theinsulating layer 16, a heat treatment (150° C. for 30 minutes) to theinsulating layer 16 is performed to completely cure the insulating layer16. As a result, the insulating layer 16 is press-bonded fixedly to thesemiconductor substrate 12, and at the same time the conductive bump 20,while it is pressed against the electrode 14, is fixed within theinsulating layer 16. In this manner, by the fourth process and the fifthprocess according to the first embodiment as illustrated in FIGS. 4A and4B, the semiconductor substrate 12 and the insulating layer 16 can bepress-bonded together while the electrode 14 and the conductive bump 20are in contact with each other, and the conductive bump 20 can beembedded in the insulating layer 16.

Then, as illustrated in FIG. 1, a rewiring pattern 18 a havingpredetermined line/space patterns is formed by processing the firstwiring layer 18 by commonly known lithography and etching techniques.After this, the insulating layer 16 and the rewiring pattern 18 a arecovered by the solder resist layer 26 so that an opening is formed in anelectrode pad forming area of the rewiring pattern 18 a. The solderresist layer 26, which functions as a protective film for the rewiringpattern 18 a, can be made of an epoxy resin or the like. The thicknessof the solder resist layer 26 according to the first embodiment is about40 μm, for instance. Then, the solder bump 24, which functions as anexternal connection terminal, is formed by a solder printing method inthe part of the rewiring pattern 18 a exposed through the opening in thesolder resist layer 26.

As described above, the semiconductor module 10 as shown in FIG. 1 ismanufactured by each step of the above-described process. By employingthe method for manufacturing the semiconductor module according to thefirst embodiment, the conductive bump 20 is exposed from the other faceof the insulating layer 16 before the insulating layer 16 ispress-bonded to the semiconductor substrate 12 on which a circuitelement is formed. Thus the circuit element is free from damage in thesecond process where laser is used. Also, by employing the method formanufacturing the semiconductor module according to the firstembodiment, the conductive bump 20 is formed on one face of theinsulating layer 16 and, at the same time, is exposed from the otherface of the insulating layer 16. And the first wiring layer 18 isprovided in a position where the conducive bump 20 is exposed, and thefirst wiring layer 18 is also provided on the other face of theinsulating layer 16 via the via contact 18 b. Accordingly, the conducivebump 20 is firmly fixed to the insulating layer 16 via the first wiringlayer 18. As a result, when the conductive bump 20 is embedded in theinsulating layer 16 by press-bonding the insulating layer 16 and thesemiconductor substrate 12 in a state where the conductive bump 20 andthe electrode 14 are disposed counter to each other, the conductive bump20 is less likely to be displaced.

Also, by employing the method for manufacturing the semiconductor moduleaccording to the first embodiment, the conductive bump 20 is formed inthe first process in such a manner that the height of the conductivebump 20 is smaller than the length of the conductive bump in thedirection parallel to the surface of the insulating layer 16. If, forinstance, the shape of the conductive bump 20 is circular, the length ofthe conductive bump 20 here may be its diameter. If, for instance, theshape of the conductive bump 20 is rectangular, the length of theconductive bump here may be the shorter side thereof. Hence, even if theforce in the direction parallel to the surface of the insulating layer16 is exerted upon the conductive bump 20 when the conductive bump 20 isembedded into the insulating layer 16, the conductive bump 20 will beless deformable. As a result, the positional error or misregistration ofthe conductive bump 20 can be suppressed.

Second Embodiment

FIG. 6 is a schematic cross-sectional view illustrating a structure of asemiconductor module according to a second embodiment of the presentinvention. In comparison with the semiconductor module 10 according tothe first embodiment, a semiconductor module 210 according to the secondembodiment differs greatly in that a glass fiber 17 is contained insidethe insulting layer 16. In the following description, the description ofthe same features as those of the first embodiment will be omitted asappropriate.

The semiconductor module 210 according to the second embodiment includesa semiconductor substrate 12 with a predetermined electric circuit or acircuit element such as MOSFET (not shown) formed by a known techniqueon a surface S (upper-face side) thereof, an electrode 14 of the circuitelement, which is part of a second wiring layer formed on the surface S(especially in the peripheral part) serving as a mounting face of thesemiconductor substrate 12, an insulating layer 16 disposed on theelectrode 14, a first wiring layer 18 disposed on the insulating layer16, and a conductive bump 20 which serves as a conductor electricallyconnecting the electrode 14 to the first wiring layer 18 in a statewhere it is embedded with the insulating layer 16.

Formed on the face of the semiconductor substrate 12 is a protectivefilm 22 in such a manner that it has a predetermined region exposing theelectrode 14. To widen the pitch of adjacent electrodes 14, a rewiringpattern 18 a is formed on the insulating layer 16 which is provided onthe top of the electrode 14 and the protective film 22. Connectionbetween the electrode 14 and the rewiring pattern 18 a is made via theconductive bump 20 connected to the exposed surface of the electrode 14and a via contact 18 b connected to this conductive bump 20. Provided ona predetermined region of the rewiring pattern 18 a is a solder bump 24,which serves as an external connection electrode, and the rewiringpattern 18 a is covered by a solder resist layer 26 except in the regionwhere the solder bump 24 is provided.

The insulating layer 16 includes therein the glass fiber 17 which is afibrous filler material. The glass fibers 17 are disposed and orientedso that the direction of the fibers thereof intersects with thedirection vertical to the surface of the semiconductor 12 (the thicknessdirection of the insulating layer 16). Use of the glass fiber 17 whosecoefficient of thermal expansion is less than that of the insulatinglayer 16 can prevent the insulating layer 16 from being deformed whenthe thermal stress is caused by the heat generated at the time thesemiconductor module 210 is activated. As a result, even though thecoefficients of thermal expansion differ greatly in between thesemiconductor substrate 12 and the insulating layer 16, the movement ofthe conductive bump 20 due to the deformation of the insulating layer 16is suppressed, so that the connection reliability can be improved. It ispreferable that the coefficient of thermal expansion of the glass fiber17 is nearly equal to that of the semiconductor substrate 12.

More specifically, the insulating layer 16 including the glass fiber 17therein is a membrane of such a type that a woven glass cloth isimpregnated with resin (glass fibers where the fibers extending in ahorizontal sheet surface direction intersect with those extending in avertical sheet surface direction, for instance). And the insulatinglayer 16 is formed on the surface S (upper-face side), and the thicknessthereof is about 80 μm, for instance. The glass fiber 17 is disposedparallel to the surface S of the semiconductor substrate 12 and providedin an approximately central part of the insulating layers 16. Thethickness of the glass fiber 17 is about 20 μm, for instance.

By a manufacturing method discussed later, the glass fiber 17 is formedin such a manner that it is in contact with a side face of the viacontact 18 b constituting part of the first wiring layer 18 and it iscurved toward the rewiring pattern 18 a in the vicinity of a side faceof the conductive bump 20. That is, as shown in FIG. 6, the glass fiber17 placed parallel to the surface S of the semiconductor substrate 12 isdeformed, in a projected manner, along with a penetration portion wherethe conductive bump 20 and the via contact 18 b penetrate. In thismanner, the glass fiber 17 is curved toward the other face 16 a of theinsulating layer 16 by the conductive bump 20 and the via contact 18 bpenetrating through the insulating layer 16. As a result, itsrestorative force works to press the conductive bump 20 against theelectrode 14 to achieve adhesion therebetween. Hence, the connectionreliability between the conductive bump 20 and the electrode 14improves, thereby producing a low-resistance connection.

The via contact 18 b penetrating through the insulating layer 16 alsopenetrates through the glass fiber 17 and therefore the via contact 18 bbecomes difficult to move. As a result, the connection reliabilitybetween the via contact 18 b and the conductive bump 20 can be improved.If a material whose coefficient of thermal expansion is close to thecoefficient of thermal expansion of silicon (Si) used generally for thesemiconductor substrate 12 is selected as the glass fiber, the thermalstress generated due to the difference in the coefficients of thermalexpansion between the insulating layer 16 and the semiconductorsubstrate 12 can be made smaller. Hence, the displacement of theconductive bump 20 can be suppressed.

(Manufacturing Method of Semiconductor Module)

Now, referring to FIGS. 7A to 9B, a method for manufacturing asemiconductor module according to the second embodiment will bedescribed. FIGS. 7A to 7C are schematic cross-sectional views forexplaining a first process in the method for manufacturing asemiconductor module according to the second embodiment. FIGS. 8A and 8Bare schematic cross-sectional views for explaining a second process anda third process in the method for manufacturing a semiconductor moduleaccording to the second embodiment. FIGS. 9A and 9B are schematiccross-sectional views for explaining a fourth process and a fifthprocess in the method for manufacturing a semiconductor module accordingto the second embodiment.

First, as shown in FIG. 7A, a copper layer 32 of about 10 μm thicknessis formed on one face of an insulating layer 16 of about 80 μmthickness, which contains therein the glass fiber 17 of about 20 μmthickness and is made of an epoxy thermosetting resin, using anelectroless plating and an electrolytic plating. Next, as shown in FIG.7B, a resist mask 34 is formed in a conductive bump forming area on thecopper layer 32, using an ordinary lithography method.

Now, as shown in FIG. 7C, a conductive bump 20 having a predeterminedcircular truncated cone shape is formed using the same method as in thefirst embodiment, and then the resist mask 34 is removed. Thus, by thefirst process according to the second embodiment as illustrated in FIGS.7A to 7C, the conductive bump 20 can be formed on one face of theinsulating layer 16.

Next, a description will be given of the second process, in which theconductive bump 20 is exposed from the other face of the insulatinglayer 16, and the third process, in which a first wiring layer 18 isformed on the exposed portion of the conductive bump 20 and on the otherface of insulating layer 16.

As shown in FIG. 8A, an opening 28 is formed by laser irradiation fromabove the insulating layer 16 in a manner such that the conductive bump20 is exposed. Here, the laser irradiation conditions are the same asthose in the first embodiment. In this manner, by the second process(exposing process) according to the second embodiment as illustrated inFIG. 8A, the conductive bump 20 can be exposed from the other face ofthe insulating layer 16.

In the second process according to the second embodiment, as shown inFIG. 5, the exposing face of the conductive bump 20 is subjected toroughening when the conductive bump 20 is to be exposed from the otherface of the insulating layer 16. Similar to the method employed in thefirst embodiment, the formation of the via hole and the rougheningprocessing of the exposed face of the conductive bump 20 can be done inthe same process. Hence, the manufacturing cost can be reduced.

Next, as shown in FIG. 8B, a plating of copper in the thickness of about20 μm is performed on the upper face of the insulating layer 16 and onthe inner face of the opening 28 including a position where theconductive bump 20 is exposed, using an electroless plating and anelectrolytic plating, as the third process. As a result, a first wiringlayer 18 comprised of a copper plating layer having a thickness of about20 μm is formed on the insulating layer 16, and at the same time the viacontact 18 b is formed inside the opening 28. As described above, apackaging board 250 as shown in FIG. 8B is manufactured by each step ofthe aforementioned process.

The exposed face of the conductor bump 20 in the packaging board 250 isroughened wherein the face thereof exposed by the above-describedprocess corresponds to a joint between the conductive bump 20 and thefirst wiring layer 18. Hence, the adhesion to the first wiring layer 18improves and therefore the displacement of the conductive bump 20 whichmay be caused when it is embedded in the insulating layer 16 can besuppressed. It is to be noted here that in the second process theopening 28 is formed from the other face of the insulating layer 16 in amanner that the arithmetic mean roughness Ra of the exposed face of theconductive bump 20, namely the face in contact with the first wiringlayer 18, is 2 to 50 μm. As a result, the adhesion between theconductive bump 20 and the first wiring layer 18 further improves.

Then, similar to the first embodiment, a semiconductor substrate 12where the electrode 14 which is the second wiring layer is formed on thesurface of the substrate is prepared as the fourth process. And, asshown in FIG. 9A, the insulating layer 16 and the semiconductorsubstrate 12 are stacked in a state where the conductive bump 20 formedon the first wiring layer 18 and the electrode 14 are disposed counterto each other. Then, in this state, press-forming is performed using thepress unit, so that, as shown in FIG. 9B, the conductive bump 20 isembedded into the insulating layer 16, thus uniting the semiconductorsubstrate 12, the conductive bump 20 and the insulating layer 16 into asingle body (fifth process). It is noted here that the press-formingcondition is the same as that in the first embodiment.

At this time, the glass fiber 17 is deformed in a projected manner dueto the force exerted from the insulating layer 16 which undergoesplastic flow. As a result, the glass fiber 17 is deformed into aprojection-like shape in a region where the conductive bump 20 and thevia contact 18 b are formed. That is, the glass fiber 17 is curvedtoward the other face 16 a of the insulating layer 16 in the vicinity ofa side face of the via contact 18 b.

Then, as illustrated in FIG. 6, a rewiring pattern 18 a havingpredetermined line/space patterns is formed by processing the firstwiring layer 18 by the commonly known lithography and etching techniquessimilar to the first embodiment. After this, the insulating layer 16 andthe rewiring pattern 18 a are covered by the solder resist layer 26 sothat the opening is formed in an electrode pad forming area of therewiring pattern 18 a. Then, the solder bump 24, which functions as anexternal connection terminal, is formed by a solder printing method inthe part of the rewiring pattern 18 a exposed through the opening in thesolder resist layer 26.

As described above, the semiconductor module 210 as shown in FIG. 6 ismanufactured by each step of the above-described process. By employingthe method for manufacturing the semiconductor module according to thesecond embodiment, the following advantageous effects are obtained inaddition to those of the first embodiment. The glass fiber whosecoefficient of thermal expansion is smaller than the coefficient ofthermal expansion of the insulating layer 16 is contained in theinsulating layer 16. Thus, the deformation of the insulating layer 16caused when the thermal stress is applied to the semiconductor modulecan be prevented. As a result, even though the coefficients of thermalexpansion differ greatly in between the semiconductor substrate 12 andthe insulating layer 16, the movement of the conductive bump 20 due tothe deformation of the insulating layer 16 is suppressed, so that asemiconductor module 210 with improved connection reliability can bemanufactured. In this manner, the glass fiber 17 is curved toward theother face 16 a of the insulating layer 16 on which the first wiringlayer 18 is provided and therefore its restorative force works to pressthe conductive bump 20 against the electrode 14 via the via contact 18 bto achieve adhesion therebetween. Hence, the connection reliabilitybetween the conductive bump 20 and the electrode 14 improves, therebymanufacturing a semiconductor module that achieves the low-resistanceconnection.

Third Embodiment

Next, a description will be given of a mobile apparatus (portabledevice) provided with the semiconductor module according to each of theabove-described embodiments. The mobile apparatus presented as anexample herein is a mobile phone, but it may be any electronicapparatus, such as a personal digital assistant (PDA), a digital videocameras (DVC) and a digital still camera (DSC).

FIG. 10 illustrates a structure of a mobile phone provided with asemiconductor module according to each of the above-describedembodiments. A mobile phone 211 has a structure including a first casing212 and a second casing 214 jointed together by a movable part 220. Thefirst casing 212 and the second casing 214 are turnable/rotatable aroundthe movable part 220 as the axis. The first casing 212 is provided witha display unit 218 for displaying characters, images and otherinformation and a speaker unit 224. The second casing 214 is providedwith a control module 222 with operation buttons and the like and amicrophone 226. Note that a semiconductor module according to each ofthe above-described embodiments is mounted within the mobile phone 211such as this.

FIG. 11 is a partial cross-sectional view (cross-sectional view of thefirst casing 212) of the mobile phone shown in FIG. 10. A semiconductormodule 10 according to each of the embodiments is mounted on a printedcircuit board 228 via a solder bump 24, and is coupled electrically to adisplay unit 218 and the like by way of the printed circuit board 228.Also, a radiating substrate 216, such as a metal substrate, is providedon the back side of the semiconductor module 10 (opposite side of thesolder bump 24), so that the heat generated from the semiconductormodule, for example, can be efficiently released outside the firstcasing 212 without getting trapped inside the first casing 212.

The present invention has been described by referring to each of theabove-described embodiments. However, the present invention is notlimited to the above-described embodiments only, and those resultingfrom any combination of them or substitution as appropriate are alsowithin the scope of the present invention. Also, it is understood thatvarious modifications, such as the order in which a packaging board or asemiconductor module is manufactured being modified as appropriate andchanges in design made in a packaging board or a semiconductor modulebased on the knowledge of those skilled in the art, and the embodimentsadded with such modifications are also within the scope of the presentinvention.

In the above-described embodiments, an example has been described inwhich the via contact 18 b is provided in such a manner as to cover theinside of the opening 28. However, for example, the opening dimension ofthe opening 28 may be narrowed, and the via contact 18 b may be formedsuch that the inside of the opening 28 can be completely filled withcopper plating by adding a suppressor and an accelerator in the platingsolution when the first wiring layer 18 including the via contact 18 bis formed. This can produce a low-resistance via contact area (theconductive bump 20 and the via contact 18 b).

Also, in the above-described embodiments, an example has been describedin which a via contact area connecting the electrode 14 of thesemiconductor substrate 12 to the rewiring pattern 18 a thereof isprovided. However, the via contact area can be applied to a connectionbetween a lower wiring layer and an upper wiring layer within amultilayer wiring substrate, for instance. In such an arrangement, theproduction stability of the multilayer wiring substrate can be improved,and the multilayer wiring substrate can be manufactured at lower cost.

1. A method for manufacturing a semiconductor module, the methodincluding: a first process of forming a conductor on one face of aninsulating layer; a second process of exposing the conductor from theother face of the insulating layer; a third process of providing a firstwiring layer on an exposed area of the conductor and on the other faceof the insulating layer; a fourth process of preparing a substrate onwhich a circuit element is formed wherein a second wiring is formed onthe substrate; and a fifth process of embedding the conductor in theinsulating layer by press-bonding the insulating layer and the substratein a state where the conductor on which the first wiring layer isprovided by said third process is disposed counter to the second wiringlayer.
 2. A method for manufacturing a semiconductor module, the methodincluding: a first process of forming a conductor on one face of aninsulating layer which contains fibrous filler material whosecoefficient of thermal expansion is small than that of the insulatinglayer, wherein the fibrous filler material is arranged so that adirection of fibers thereof intersects with a thickness direction of theinsulating layer; a second process of exposing the conductor from theother face of the insulating layer; a third process of providing a firstwiring layer on an exposed area of the conductor and on the other faceof the insulating layer; a fourth process of preparing a substrate onwhich a circuit element is formed wherein a second wiring is formed onthe substrate; and a fifth process of embedding the conductor in theinsulating layer by press-bonding the insulating layer and the substratein a state where the conductor on which the first wiring layer isprovided by said third process is disposed counter to the second wiringlayer.
 3. A method for manufacturing a semiconductor module according toclaim 1, wherein a means for roughening an exposed face of the conductoris used in said second process.
 4. A method for manufacturing asemiconductor module according to claim 3, wherein laser is used as theroughing means, a via hole having a larger diameter than a spot diameterof the laser is formed from the other face of the insulating layer andthe exposed face of the conductor is roughened by a plurality of laserirradiations.
 5. A method for manufacturing a semiconductor moduleaccording to claim 3, wherein in said second process an opening isformed from the other face of the insulating layer in a manner such thatan arithmetic mean roughness of the exposed face of the conductor is 2to 50 μm.
 6. A method for manufacturing a semiconductor module accordingto claim 1, wherein in said first process the height of the conductor ina direction vertical to the face of the insulating layer is smaller thana length of the conductor in a direction parallel to the face of theinsulating layer.
 7. A method for manufacturing a packaging board, themethod including: a first process of forming a conductor on one face ofan insulating layer; a second process of exposing the conductor from theother face of the insulating layer; and a third process of providing awiring layer on an exposed area of the conductor and on the other faceof the insulating layer, wherein a means for roughening an exposed faceof the conductor is used in said second process.
 8. A method formanufacturing a packaging board according to claim 7, wherein in saidfirst process the insulating layer contains fibrous filler materialwhose coefficient of thermal expansion is smaller than that of theinsulating layer, the fibrous filler material being arranged so that adirection of fibers thereof intersects with a thickness direction of theinsulating layer.
 9. A method for manufacturing a packaging boardaccording to claim 8, wherein laser is used as the roughing means, a viahole having a larger diameter than a spot diameter of the laser isformed from the other face of the insulating layer and the exposed faceof the conductor is roughened by a plurality of laser irradiations. 10.A method for manufacturing a packaging hoard according to claim 7,wherein in said second process an opening is formed from the other faceof the insulating layer in a manner such that an arithmetic meanroughness of the exposed face of the conductor is 2 to 50 μm.
 11. Amethod for manufacturing a packaging board according to claim 7, whereinin said first process the height of the conductor in a directionvertical to the face of the insulating layer is smaller than a length ofthe conductor in a direction parallel to the face of the insulatinglayer. 12-18. (canceled)